This discussion assumes certain definitions of terminology:

• natural number : A positive integer; an integer 1 or greater.
• prime number : A natural number with exactly two distinct natural factors, 1 and itself. In particular, 2 satisfies this requirement despite being even, while 1 does not satisfy this requirement because it has only one such factor instead of the required two.
• multiset : A generalization of a set wherein the multiplicity of each item is significant.

The natural number indicated by a given multiset is the product of 1 and each element of the multiset. For example, 1 is represented by the empty multiset {∅}, 3 by {3}, 5 by {5}, 15 by {3,5}, 25 by {5,5}, and so on.

Multiset operations on the multisets correspond to other operations on the natural numbers they represent:

• Intersection (i.e. retaining the lesser multiplicity per element) is equivalent to finding the greatest common divisor (gcd):
  • gcd(54, 24)
  • {2, 3, 3, 3} ⋂ {2, 2, 2, 3}
  • {2, 3}
  • 6
• Union (i.e. retaining the greater multiplicity per element) is equivalent to finding the least common multiple (lcm):
  • lcm(8, 12)
  • {2, 2, 2} ∪ {2, 2, 3}
  • {2, 2, 2, 3}
  • 24
• Addition of the multiset (i.e. retaining the sum of multiplicities per element) is equivalent to multiplication:
  • 414 * 555
  • {2, 3, 3, 23} + {3, 5, 37}
  • {2, 3, 3, 3, 5, 23, 37}
  • 229770
• Subtraction of the multiset (i.e. retaining the differences of multiplicities per element between one set and another) is equivalent to division:
  • 88088 / 2002
  • {2, 2, 2, 7, 11, 11, 13} − {2, 7, 11, 13}
  • {2, 2, 11}
  • 44
  • Note that this division is not closed on natural numbers unless the result would also be a natural number (i.e. the left operand must be divisible by the right) because the multiset subtraction itself is not closed on multisets (with nonnegative multiplicities). The multiset notation can still help to reduce the fraction to lowest terms:
  • 2310 / 273
  • {2, 3, 5, 7, 11} − {3, 7, 13}
  • {2, 5, 11} − {13} (since the multiset can’t have negative multiplicities, this is the simplest form)
  • 110 / 13
• Multiplying all of the multiplicities in the set by n yields the number to the nth power:
  • 168⁴
  • {2, 2, 2, 3, 7} multiplicities multiplied by 4
  • {2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 2, 3, 3, 3, 3, 7, 7, 7, 7}
  • 796594176
• If all of the multiplicities in the set are themselves divisible by n, dividing them yields the nth root of the number:
  • ∛474552
  • {2, 2, 2, 3, 3, 3, 13, 13, 13} multiplicities divided by 3
  • {2, 3, 13}
  • 78
• Meanwhile, the natural-to-multiset transform won’t help you at all with addition and subtraction.

This circuit provides a pulse-sequencing capability using the control voltage inputs of the 555.

The circuit described here triggers three (or an arbitrary number) monostables with differing but related widths. What’s different about this one than others I’ve seen is that this circuit has only one timing signal; in particular, there is only one RC network among all, which could potentially reduce the parts count and, more importantly, increase consistency among the timers.

The timing network is actually sort of a modified RC using a transistor and a voltage reference to charge the capacitor with a constant current. The timing is determined by the base voltage of the PNP transistor, the resistance at the emitter resistance, and the capacitance at the collector. The voltage drop across the resistor is the V_cc – V_b + V_eb^[1]. As long as none of these three values vary significantly in the application, the resistor’s voltage drop can be considered constant. If the resistor is, as expected, also constant, then the current through it is constant as well: I = V/R. The transistor will adjust as necessary, if possible, to maintain that current through the transistor^[2]. If the supply voltage is well regulated, the base voltage can be set with a voltage divider.

The output of this constant current timing network, in contrast to the tricky curve of a regular RC network, is a linear ramp. This makes it easier to calculate the desired control voltage for each monostable. In the example above, the control voltages are 1V, 2V, and 3V, where the 1V and 2V timers produce a pulse exactly 1/3 and 2/3, respectively, the width of the 3V timer pulse. The values need not be this regular. A normal RC network could be substituted if you’re willing to do the math.

The monostable with the longest delay should have its discharge pin connected with its threshold pin in order to discharge the capacitor.

This approach gets a little unfortunate where setting the control voltages comes in. The CV is preset internally with a three-step resistor divider network. The CV itself is roughly 5k from V_cc and roughly 10k from ground. If I’ve done the math correctly, this is equivalent to a 2Vcc/3 supply through a 3.3k resistance. This means that you can’t trivially set the control voltage with a divider—something with a low (ideally zero) output resistance is necessary. Here are some things that might be worth trying:

• Resistor divider with proper buffer (2 resistors, 1/4 to 1 op amp IC). If you’re not willing to complicate the calculations, an op amp can output the same voltage as the input, with no base-emitter drop. As a bonus, it’s an op amp, which is capable of a whole lot more. If restricted to Radio Shack, I’d pick up two TL082 JFET dual amps (or an LM324 quad if they’re out), then use three of the amps with a resistor ladder to set CVs and the one left over to upgrade the current source. I’d guess this is the option that would involve the least hair-pulling. (Edit: An example of a buffered resistor divider, complete with redone current source, in terms of a 7805 voltage regulator. Would require a supply voltage above 7 volts or so, but it’s an easy out in 2-3 ICs and about 10 resistors, plus the transistor and RC already in the circuit.)
• Resistor divider with unity gain transistor (2 resistors, 1 NPN transistor). Similarly to the current source, the emitter voltage is a nearly fixed drop below the base voltage.
• Trimmer (1 potentiometer, potentially up to 2 biasing resistors) if you’re okay with a bit of tuning.
• Linear voltage regulators/references. Would probably work really well, but might be expensive depending on where you buy^[3] and in this case requires a fairly small one (probably around 1V). The LM317 can be treated as a precision 1.25V drop, as long as the minimum load requirement is met.
• Diode drops (1 diode). In the simulator, I was able to get the circuit to work with a ladder of diode drops for the control voltages (i.e., around 0.7, 1.4, and 2.1V). I’ve read that in practice this doesn’t work nearly as well.

By the way, the intended purpose is to trigger some D flip-flops to read serial data in an experimental line encoding I’ve conceived. It’s a variation of one I discussed way back, but the initial rising edge is followed by three bits of data before the mandatory fall. If it works, it could mean a simple output interface for PCs (e.g. via monitor or sound card) to devices that only understand data in terms of data, clock, and latch. What does this mean? You guessed it—semi-headless 74HC595 displays. (Okay, maybe not so much, but that’d at least be a good way to test it.)

This circuit is available on the Falstad simulator.

1. ^[1] V_eb may vary slightly depending on current, but is roughly 0.7V under normal circumstances. ↩
2. ^[2] Up to near the max collector voltage, in this case slightly lower than the emitter voltage. ↩
3. ^[3] LM317 is $3 at Radio Shack, but way cheaper online, especially in a TO-92 package. ↩

Almost as fun as it looks.

Print your own, if you’d like!

This octahedral toy/tool/thing represents manipulations on a logic gate with two inputs A and B and one output Y. A face of the object says what operation it executes, such as “AND”. From there, each side of the face is marked with a variable—A, B, or Y—and rotating past that edge shows you the result of inverting that variable.

For example, if I start at AND, I might turn past Y to NAND (AND with inverted output). Then, I might turn past A to IF (another name for OR NOT), because that’s what /A NAND B is. Finally, I might turn past B to OR, since that’s A OR NOT /B.

Alternatively, you might choose a starting point and an ending point, then trace the path between them to determine how many inverters are necessary to do the conversion.

Note that any face is at most three turns from any other. Polar opposites such as AND and OR are on opposite faces, and changing one to the other involves inverting each input and the output.

The somewhat uncommon logical operator names IMP (short for IMPLIES), NIMP, IF, and NIF appear as one-word substitutes for operations that invert B (NAND NOT, AND NOT, OR NOT, and NOR NOT, respectively). The two-word versions appear as a subtitle.

This isn’t quite as great as it could be. The text sizes and layout need a lot of work; the expression text is only barely big enough to read. However, since the time may never come for improvement, here it is for you to play with.

Enjoy!

Skip this bit if analog creeps you out: The 555 timer has some analog circuitry that seems to be used in the majority of its applications. There is a control voltage (CV) pin that sets thresholds for comparators at the TH (threshold) and /TR (trigger) pins. If TH is above CV, then it registers as high (low otherwise); if /TR is below CV/2, then it registers as low (high otherwise). CV can be set externally^[1], but usually it’s left alone, and its default setting is CV = 2V_cc/3 (making CV/2 = V_cc/3).

Really, that’s where the analog part ends. The rest is basically digital, and digital is far more comfortable for those of us from the computer side of the house. The 555 timer is basically an RS latch with mildly analog inputs, plus a preemptive additional reset (/RST). I realized that’s still vague for my taste, so I scribbled out a bunch of notes, drew up some tables, and eventually came up with the following logical equivalent of the 555:

Even if you ignore for a moment the tweakable threshold voltage settings on the threshold and trigger inputs, the 555 has interesting possibilities as a digital circuit.

(Edit: A demonstration of the above on Falstad.)

The chip has three logical inputs. One, /RST, is a legitimate TTL input that is inverted. The others feed into comparators as just described, but ignoring the level details, TH simply feeds into a buffer and /TR pin feeds into an inverter. There are also two outputs, OUT (output) and DIS (discharge) pin. Both carry the same data, but OUT is driven as a logic level while DIS is open-collector^[2].

If you ignore the /RST, the 555 is an R-/S latch, where TH and /TR pins serve as R and /S, respectively. If both of those signals are active, the result is by definition undefined.

/RST adds to this an overriding additional reset signal. When active, the output is defined as low even if /TRis also active.

By extracting the behavior of a plain RS latch from this, the relationship among the inputs is clarified:

• The latch is set if /TR is low and /RSTis high.
• The latch is reset if THis high, /RSTis low, or both.

Some degenerate cases:

• As noted before, if /RST is high then TH and /TR form an R-/S latch.
• If TH is low, then /RST and /TR form a kind of R latch^[3], with /RST and /TR as /R and /S, respectively.
• If TH and /TR are tied together as a single input, and /RST is used as another input, the result is an “AND NOT” logic gate, with TH+/TR as the inverting input and /RST as the non-inverting input.
• The inverting input is effectively Schmitt-triggered, with the hysteresis zone set between CV/2 and CV. (/RST remains a normal TTL input.)
• With /RST tied high, this becomes a Schmitt-triggered inverter.

Of particular interest is the R latch. This particular latch is set when /TR is low and /RST is high. On the other hand, this latch is reset when /RST is low with no other condition. When I saw this it seemed a bit familiar, like /RST being high enables the value of /TR having any impact.

So, I prepared a truth table for the D and E lines of a D latch, and entered the corresponding values of /R and /S. The result: /S = /E, and /R = D or /E.

My first conclusion is that, if you’re not bound to using only 555 elements, this could make things a lot easier. It requires an active-low /E, if that can’t be accomplished anywhere else, an NPN inverter (one transistor, two resistors) will suffice. /E is fed directly into /S, and a diode-logic OR gate (2 Schottky diodes, one resistor) figures /R. Even with the inverter that’s way fewer parts than yesterday’s solution.

In four parts, a D latch with active-low enable. Slap an inverter (also pictured) onto the front to make it a normal enable.

(Edit: A demonstration of the above on Falstad.)

Translating the setup to all 555s is trickier. If you can set up for active-low both /E and /D, it’s possible to get it down to three elements: The latch, an inverter into /R, and an AND NOT gate. This follows from the proposition that R = /D and E = /D and not /E. Then, /R = not R. And, of course, for active-high D you add an inverter—4 elements, no better than yesterday.

The difficulty is that the only gate a single 555 can simulate (other than an inverter) is an AND NOT. While it’s possible to make any other gate from AND NOT parts, some take more fudging than others. To make the OR gate we’d like, you need three. My derivation^[4] is as follows:

• A OR B
• NOT (A NOR B)
• NOT ((NOT A) AND NOT B)
• NOT ((1 AND NOT A) AND NOT B)
• 1 AND NOT ((1 AND NOT A) AND NOT B)

Note that in the last stage there are three “AND NOT”s and no other operators. Note also that, using (Schottky) diode logic, the parts count is the same: Two diodes and one resistor. Guess which one I’d rather breadboard.

1. ^[1] Its default value comes from a resistive divider of approximately 5K vs. 10K, so if the value is critical it’s probably better to set it via a lower impedance, such as with a voltage reference or a (unity gain) buffer. ↩
2. ^[2] 0V on low, high-impedance on high. ↩
3. ^[3] An RS latch that favors R in a tie ↩
4. ^[4] Through repeated application of DeMorgan’s laws. ↩

No guarantees, but it worked in the simulator.

Today, figured out how to make a (possibly low-speed) transparent D latch out of an R-/S latch, plus a couple of logic gates, and an inverter. Each of these four things can be constructed from a 555 timer (or half of a 556). Alternatively, each of the gates can be replaced by three diodes^[1] and a resistor, and the inverter by an NPN transistor and a resistor. Not pictured is the AC coupling^[2] on the E input that would make this an edge-triggered flip-flop instead of a latch.

The significance of this is that a D flip-flop, a 1-bit static RAM and an important element of sequential logic, can be constructed very easily with stuff readily available from Radio Shack, which doesn’t stock logic ICs anymore but does carry 555s and 556s (as well as diodes, resistors, and transistors). Naturally, I have the best interests of the impatient experimenter in mind. :-)

1. ^[1] With Schottky diodes you could probably get away with omitting the output diode. ↩
2. ^[2] In this case, an RC highpass is used, an inline capacitor of about 0.1µF followed by a 10kΩ pull-down resistor. ↩

How to do simple math on real numbers in a very non-digital way.

If you can represent the scalar terms of an arithmetic expression as voltages and/or resistances, then many operations can be performed with op amps (which is, incidentally, what the “op” part means). Several of the major features are described above.

• The word “amp”, for amplifier, refers to the fact that the device amplifies, or enlarges, an input signal by a factor called gain which is represented by the letter A^[1] When A is fixed, the amplifier serves to multiply the input signal by A. By default, A is ideally infinite^[2], but can be set to a fixed value using resistors.
• Division (not pictured) can be performed using a resistor divider network. No op amp is required, though using one might be desirable to avoid loading effects.
• “Subtract then multiply by A > 0″: An op amp’s natural mode (in my opinion, anyway) is the differential amplifier. Two voltages are input; V₂ is subtracted from V₁, and then the difference is multiplied by A, which is based on the ratios of resistors used. All other linear modes pictured can be described in terms of this one:
• “Multiply by A >= 1″: If you take the divider off of V₂ and replace it with V_in, it’s equivalent to setting V₂ to V_in(1 + R_in/R_F). Then, just set V₁ to 0. The result is A(V₂ – V₁) = (R_F/R_in)V_in(1 + R_in/R_F) = V_in(1 + R_F/R_in).
• “Multiply by A < 0″: Let V₂ = 0, V₁ = V_in. The result is A(V₂ – V₁) = (R_F/R_in)(0 – V_in) = V_in(-R_F/R_in).
• “Add then multiply by A < 0″: Exactly the same as the previous case, except that the input is from a resistor divider network. If V₁ and V₂ are fed to the same point through equal resistances as shown, it’s equivalent to a single input of V_X = (V₁ + V₂)/2 through a resistance of R_X = R_in/2. With the other input at 0, the result is A(0 – V_X) = (R_F/R_X)(-V_X) = -(2R_F/R_in)((V₁ + V₂)/2) = -(R_F/R_in)(V₁ + V₂).
• “Logarithmic” and “Exponential”: An NPN transistor with a grounded base can be placed either at the feedback or the input to implement a logarithmic or exponential output, respectively. The coefficients of the expression are not well defined, since they vary from instance to instance, but if the transistors used are closely matched and thermally linked (for example, in a single-chip transistor array) then with some tuning their outputs will be consistent. A log transform can be used to easily multiply (by adding logarithms) or divide (by subtracting logarithms) two voltages.
• Comparison (not pictured): As discussed here previously, a comparator is a sort of op amp specialized to output only logical high/low depending on whether the value at the non-inverting input is higher than the value of the inverting input, outputting high and low, respectively. In a pinch, an op amp will do the same thing in the open-loop configuration—direct inputs and no feedback, resulting in the extremely high gain mentioned earlier. If the non-inverting input is even slightly different than the inverting input, that small difference is amplified so immensely that the output will be either the highest possible or the lowest possible, meaning around the positive and negative supply voltages, respectively. Use of an actual comparator is preferred though, since it is better tuned for digital use.

1. ^[1] The “A” presumably refers to “amplification”. ↩
2. ^[2] But in practice is just a very high number. ↩

This circuit has not been tested. It might work. It might not. Who knows? All diodes should probably be Schottky.

I contrived a diode-transistor logic (DTL) circuit for a SR latch^[1] with a CMOS push-pull output and a break-before-make mechanism to prevent simultaneous push and pull (shoot-through). I have no idea whether it actually works and there are probably easier ways to do it, but it was kinda fun.

The upper schematic lays out the concept in terms of OR gates with different inversions (clockwise from upper left: NOR, OR, AND, NAND). The output is fed back into the inputs through diode-resistor level shifts so that the one being fed into the high side is high when the output is high but low if the output is either low or off (high-impedance), and the one into the low side is low when the output is low, but high if the output is high or off. This feedback should prevent either output FET from turning on until the complement is turned off (or close to off).

The lower schematic is the upper schematic rendered in diode-transistor logic. The lower-left gate, a NAND, is implemented using the textbook DTL NAND with an NPN transistor. The NOR in the upper left is actually the same as the NAND, but with the diodes reversed and a PNP on the output. Note that in both cases the feedback diode-resistor shift is now part of the gate itself. The other two gates are just diode logic since OR (upper right) and AND (lower right) can be implemented without a transistor on the output.

This contrivance is for a power logic buffer; the intended supply voltage would be somewhere from 12 to 48 volts and the current capacity on the output MOSFETs would be at least a couple of amps. I haven’t tested the thing. Please don’t use it, except in test circumstances, unless you know what you’re doing.

1. ^[1] Technically, an S AND NOT R latch. ↩

One of the common uses of an op amp is as a “unity gain” buffer, meaning that the output voltage is as close as possible to being the same as the input voltage. At a glance this might seem like a trivial thing, but it’s used to great advantage.

For example, a resistive voltage divider can be used to derive some fraction of a larger voltage by representing the ratio with resistors. Given a 9V supply, a divider over 100K and 47K would yield about 2.9V (9V * 47K/(100K+47K)). Unfortunately, this is of only limited use directly, since driving a load from the output causes that voltage to drop. This happens because the load itself acts as a resistor to ground in parallel with the divider, changing its resistance.

The divider does okay, though, feeding to a high-impedance input (i.e., one that doesn’t pull a lot of current). The inputs on an op amp fit that description, and its output is low-impedance (meaning that it can supply current without trouble). That’s a huge part of why op amps are useful. If you take the resistive divider’s output into the non-inverting (“+”) input of an op amp and the amp’s own output into the inverting (“-”) input, you get a unity gain buffer, an amplifier that outputs the same amplitude as the input (“unity gain” refers to the 1:1 ratio of input to output). The buffer continuously compares its output to the input. If the output is too high, it’s lowered; if too low, it’s raised.

In general, the op amp’s job is to perform an analog computation on its inputs that amounts to subtraction followed by multiplication. It subtracts the voltage of the inverting input from the voltage of the non-inverting input, then multiplies it by a factor called gain. By default, the gain is an arbitrarily high number called the open-loop gain of the amp. However, by feeding the output back into the inputs in different ways, it’s possible to fix the gain to a more useful value, such as 1 in the above scenario.^[1]

Anyway, this ability to continuously adjust an output to a certain point reminded me of linear voltage regulators, like the 7805 and the LM317. I hypothesized that these 3-terminal regulators are basically heavy-duty op amps with a fixed voltage reference on one of the inputs. A little research confirmed this.

A linear voltage regulator is a voltage reference stuck to an op amp with high output current capability. Now you know—and knowing is half the battle.

[Note: The above image replaces a previous version that was less accurate.]

The data sheet for the fixed 7805 (and other 78xx) regulators suggested a circuit that allows the use of the regulator in an adjustable mode for voltages higher than the nominal voltage. Under normal circumstances, the regulator simply adjusts the output pin to be exactly 5V above the ground pin. In this mode, the ground pin is not tied to ground. Instead, the output and ground pin are placed across the high side of a resistive divider. The regulator fixes the voltage across the upper resistor to its face value. The lower resistor gets all of the current from the upper resistor, plus the garbage quiescent current from the machinery in the device. Multiplying this sum by the lower resistance yields, via Ohm’s law, the voltage across the lower resistor. The sum of that voltage and the regulated voltage is the output.

The data sheet for the LM317 shows a circuit essentially identical to the one described above with a few name changes. In fact, the ’317, when used in the 7805′s nominal configuration, is itself a fixed 1.25V^[2] regulator.

Knowing that these regulators are so alike, then, why should we ever choose ’317 over 7805? The answer: ’317 has a subtle difference that makes it far more suitable in its adjustable mode: The current out of its adjustment terminal is a couple of orders of magnitude smaller^[3], enough smaller in fact that it could be disregarded in many cases when calculating V_out. This is especially useful in cases where the application doesn’t adjust the output voltage, but that requires a regulator for an awkward voltage (like the 13V programming voltage of a PIC). Using a 7805 in such an application might require a trimmer to fine-tune the output, while the ’317 would probably be okay with a fixed-value resistor instead.

Pictured are the much simplified equivalent schematics, plus my derivation of how V_out is calculated. R₂I_adj should be dominated by the rest of the expression.

1. ^[1] Incidentally, a comparator is basically a specialized op amp that has been optimized to only output high or low (i.e. in the logical sense). It works as specified above, but boils the problem down to “is the non-inverting input greater than the inverting input?” yielding high if so and low if not. An op amp can be used as a comparator, but actual comparators do the job faster and better. ↩
2. ^[2] 1.25V is less arbitrary than you might think: It is the output of a silicon bandgap reference, which is designed to be steady and reliable in spite of temperature and environmental changes. Cool. ↩
3. ^[3] 7805 I_Q is 5mA typ., LM317 I_adj is 50µA typ. ↩

An important building block in sequential logic. Remembers whether it is on or off.

For reasons explained elsewhere in detail^[1], iPods (and iPhones, etc.) newer than the oldest generations refuse to charge if all you give them is a USB port with the power lines connected and the data lines disconnected. Presumably, it has partly to do with the fact that some of the newer devices can negotiate for more than the 500mA upper limit of USB proper, and possibly that the additional requirements hinder the proliferation of unlicensed peripherals, if only temporarily, so that Apple has an easier time pushing their own.

Fortunately, there’s no actual (digital) data transfer going on. To make the charger visible to the device, a bit of static information is provided on the data lines. Each data line can be held to a voltage as low as 0V (ground) or as high as about 3.3V (USB nominal logic high). Simply setting the lines to some combination of these high and low values^[1] reports to the device that it can provide 100mA or 250mA for charging. Newer devices look for cues between high and low; the device reports that it can supply 500mA by holding both data lines at around 2.0V, or 1000mA (1A) by holding D+ to 2.0V and D- to 2.8V. The latter two configurations are what the schematic describes.

This charger should also generally be okay for other USB-charging devices; nothing going on with the data lines is in principle electrically unsafe for a USB device.

1. ^[1] ladyada’s notes on iPod chargers’ finicky requirements ↩